Recent miniaturization of semiconductor devices has made it possible to fabricate a cutting edge semiconductor device having a larger number of semiconductor elements on the substrate thereof. When the semiconductor elements on the substrate of the semiconductor device are connected each other, it is insufficient that the semiconductor device is configured as a single wiring layer. For this reason, a so-called multi-layer wiring structure, which is configured by layering a plurality of wiring layers via inter-layer insulation films, is adopted to configure such a semiconductor device.
In particular, multi-layer wiring structures in accordance with a so-called dual-damascene method have been vigorously studied and developed in recent years. In the dual-damascene method, grooves as wiring portions (hereinafter which are referred to as “wiring grooves”) and holes as via contacts (hereinafter which are referred to as “via holes”) are formed in an inter-layer insulation film in advance, and a wiring layer is formed by filling a conductive material into the wiring grooves and the via holes.
The dual-damascene method has many variations. Japanese Laid-Open Patent Application No. 2000-124306 discloses a method of fabricating a semiconductor device by using an inter-layer insulation film. FIGS. 1A through 2D show such a method of fabricating a multi-layer wiring structure having a dual-damascene structure by using an inter-layer insulation film.
Referring to FIG. 1A, a first wiring pattern 11 of Cu is formed on a substrate 10 via an insulation film (not illustrated), and an SiN film, which serves as a barrier film 12, is formed on the wiring pattern 11. Then, an organic SOG film, which serves as a first inter-layer insulation film 13, is formed on the barrier film 12. In addition, an SiO2 film, which serves as an insulation film 14, is formed on the first inter-layer insulation film 13.
Furthermore, a second inter-layer insulation film 15 is formed on the insulation film 14. Then, two-layer structured hard mask films 16 and 17 are formed on the second inter-layer insulation film 15. Specifically, the first hard mask film 16 is formed of SiN of about 20 nm in thickness, and the second hard mask film 17 is formed of SiO2 of about 100 nm in thickness. These hard mask films 16 and 17 are often called etching stoppers.
After formation of the second hard mask film 17, a resist pattern 20 having an aperture 20A corresponding to a wiring groove that is expected to be formed in the second inter-layer insulation film 15 is formed on the second hard mask film 17 at the fabrication step shown in FIG. 1B. In order to pattern the second hard mask film 17, dry etching using a CF4/Ar material is performed on the second hard mask film 17 by using the resist pattern 20 as a mask at the fabrication step shown in FIG. 1C. Subsequently, the resist pattern 20 is removed through ashing. Through patterning on the second hard mask film 17, an aperture 17A corresponding to the aperture 20A is formed in the second hard mask film 17. In this configuration, the first hard mask film 16 is exposed via the aperture 17A.
As shown in FIG. 1D, a resist pattern 21 having an aperture 21A corresponding to a via hole that is expected to be formed in the first inter-layer insulation film 13 is formed. At the fabrication step shown in FIG. 1E, the first hard mask film 16 is patterned by using the resist pattern 21 as a mask, and then the second inter-layer insulation film 15 is dry-etched. At this time, the insulation film 14 works as an etching stopper. Subsequently, the resist pattern 21 is removed through ashing or the like.
At the fabrication step shown in FIG. 2A, an exposed portion of the first hard mask film 16 is removed through dry etching by using the second hard mask film 17 as a mask. At the same time, the insulation film 14 is also removed.
At the fabrication step shown in FIG. 2B, the first and second inter-layer insulation films 13 and 15 are patterned through dry etching by using the remaining portion of the second hard mask film 17 as a mask. At the same time, a wiring groove 25 and a via hole 26 are simultaneously opened. At this time, the insulation film 14 works as a mask for forming the via hole 26.
At the fabrication step shown in FIG. 2C, an exposed portion of the barrier film 12 under the via hole 26 is removed through dry etching. At the fabrication step shown in FIG. 2D, a Cu film 30 is accumulated to fill the via hole 26 and the wiring groove 25 of the configuration shown in FIG. 2C, and then an extra portion of the Cu film 30 on the second hard mask film 17 is removed in accordance with a chemical machine polishing (CMP) method. As a result, it is possible to form a Cu wiring pattern that properly fills the via hole 26 and the wiring groove 25.
However, the above-mentioned method of fabricating a semiconductor device has many fabrication steps, resulting in an adverse effect on yield of the semiconductor device. As a result, it is impossible to prevent an increase in fabrication cost of the semiconductor device.